Implementations of the claimed invention generally may relate to the field of multi-channel mass storage devices, and in particular to a error correction in such devices.
Mass storage devices may include a number of memory devices, such as NAND memory devices, NOR memory devices, phase change devices, magnetic media devices, optical storage, etc., that typically include single-channel (i.e., one per memory device) controllers. Such single channel device controllers typically include error correcting code (ECC) encoding and decoding just before the data is being written to the storage device.
ECC encoding typically produces so-called check bytes that are typically stored in a designated location in the memory device. These check bytes may be used to correct data errors resulting from data storage in the device when reading data out of the storage device.
In such a per-channel ECC scheme, the check bytes are typically associated with a sector size (i.e., a specifically-sized division of a storage device) that is native to the memory device. Also, the type or strength of the ECC algorithm used may be limited by a size of the designated location in the memory device for storing the ECC check bytes. These characteristics may not be desirable when designing multi-channel mass storage devices.